1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to an electrically erasable programmable read only memory circuit.
2. Description of the Prior Art
Electrically erasable programmable read only memory (EEPROM) finds a wide variety of uses in the electronics industry. They can be used as stand alone memories, such as used with microcomputer systems and controllers. EEPROM memory may also be embedded into various types of user programmable devices, many of which are referred to generally as field programmable logic devices.
EEPROM memory cells can be used in some types of programmable logic devices to store configuration information for such devices. They are also used to define switch connections in an AND-OR array, such as used in programmable logic arrays and more sophisticated devices which are programmed in a similar way.
EEPROM cells, each containing a memory bit, are programmed ON using a high voltage signal to inject charge onto a floating gate. These cells are programmed off by reversing the polarity of the high voltage, and removing charge from the floating gate. Once programmed, the charge on the floating gate causes the floating gate device to behave as a field effect transistor which remains switched either on or off.
The higher voltages needed for programming EEPROM cells require physically larger transistors in other parts of the device which also encounter these higher voltages. These larger devices are necessary in order to avoid hot electron effects and punch through as known in the art. These larger transistors operate at a slower speed than smaller ones, decreasing the overall operating speed of the device.
Read/write transistors used to access the floating gate transistors are among those which must be able to handle the higher programming voltages. In addition to their larger size, the circuitry used to drive these transistors must be fabricated using N-channel technology. CMOS circuitry cannot be used to drive the read/write transistors because the higher voltage used therein makes the drive circuitry more susceptible to latch-up problems. Since N-channel technology is used in the driving circuitry, the maximum signal which can be applied to turn on the read/write transistors during normal operation is V.sub.cc -V.sub.Tn. This lower driving voltage provides less signal margin for the read/write transistors, and results in slower operation. Bootstrapping can be used to raise the signal back to V.sub.cc, but the necessary circuitry adds delay.
The design of current EEPROM cells results in undesirable capacitive loads, especially as used in an AND-OR array on a programmable logic device. These capacitive loads increase the switching time of the programmable logic device, reducing its performance.
It would be desirable to provide an EEPROM cell which overcomes many of the important limitations described above. It would be desirable for such a cell to provide improved performance while being compatible with current process technology.